integrated (Total 281930 Patents Found)

Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-...
A method of position-based integrated motion controlled curve sawing includes the steps of: transporting a curved workpiece in a downstream direction on a transfer, and monitoring position of the workpiece on the transfer, scanning the workpiece through an upstream scanner to measure workpiece profiles in spaced apart ...
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum ...
Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the p...
Device to change the equipment on a compact rolling block (11) consisting of an integrated plurality of rolling stands with pairs of rolls supported as cantilevers with alternate roll axes, a complete change of the equipment taking place substantially at one and the same time on all the stands, the equipment being deli...
A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedur...
An integrated electronic control circuit comprises a microcontroller connected to at least one volatile memory, at least one input/output port, a plurality of control devices, and an electronic non-volatile memory device comprising a non-volatile memory cell matrix linked to a control register, and a switch element con...
An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ ...
An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers ...
The present invention introduces methods for implementing gridless non Manhattan architecture for integrated circuits. In one particular embodiment, an integrated circuit layout containing horizontal, vertical, and diagonal interconnect lines is first created. Next, the integrated circuit layout is then compacted. The ...
In an integrated optical arrangement, such as a photoelectric position measuring arrangement, a diffraction grid is scanned by light beam diffraction by a scanning unit having a laser. A light beam bundle emanating from the laser is split by the diffraction grid into two diffraction beam bundles, which are inserted int...
A frame assembly for a light shutter including a frame structure for enclosing an electro-optic shutter assembly, the frame structure having a front surface which can be positioned opposite a cover lens, and a switch for controlling an operation mode of the electro-optic shutter assembly, the switch being mounted on th...
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is ...
A radio (100) having an integrated transceiver circuit (102) avoids circuit crosstalk through the use of a clock shifter circuit (120). The radio includes a microcontroller unit (MCU) (104) controlled by a MCU clock. A channel selector (116) coupled to the MCU (104) provides a selected frequency channel while memory (1...
A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an i...
A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric material and enclosed within an isolation structure of an electric...
In a signal delay time calculation method of calculating an approximate signal delay time in an LSI based on AWE in which a signal voltage waveform is calculated by using terms of an admittance up to n-th order obtained by Laplace transform for the LSI. Even if there are one or more poles of the signal having a real-nu...
A metal-containing refractory sulfide ore is split into a first portion and a second portion. The first portion is partially biodigested by a sulfide-digesting microorganism in a biooxidation reactor where the microorganism is acclimated to the sulfide "diet" provided by the ore. The partially digested ore is t...
A method for packaging an integrated circuit device includes forming a dielectric support layer on the surface of a substrate wherein the dielectric support layer includes an opening therein exposing at least a portion of an active region of the substrate. A protective layer is provided on the dielectric support layer ...
An integrated circuit (IC) package includes an IC having at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conduc...
A method for planarizing the surface of a semiconductor wafer is disclosed. It involves the steps of: (a) applying a coating solution containing a polymeric material on a semiconductor wafer having a non-planar surface; (b) curing the polymeric material to cause the polymeric material to become a hardened polymeric mat...
A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of ...
A BGA (Ball-Grid Array) integrated circuit package is proposed, which is incorporated with a palladium-coated heat-dissipation device to help enhance the thermal conductivity of the integrated circuit package and make the manufacture more cost-effective to implement. The heat-dissipation device includes a base block ma...
This invention provides a means of achieving the close control of iodine flow rate, temperature of the resulting combined gaseous mixture of iodine in diluent gas, as well as the rapid start and stop response time needed for full-scale laser operation. It comprises an iodine charge stored as a solid and is heated to co...
A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and ...
A method for the construction of a highly integrated semiconductor connecting device. In the semiconductor connecting device, a plurality of third conductive lines are connected with a plurality of first conductive lines formed in the active regions of a semiconductor substrate through contact holes formed on the activ...
A novel heterojunction acoustic charge transport device (HACT) includes a modulation doped field effect transistor (MODFET) on the same substrate. The device is characterized by a sequence of epitaxial layers such that the MODFET is fabricated in a first portion of the uppermost layers while the HACT device is fabricat...
A method for additively de-marking a packaged integrated circuit die bearing engraved marking indicia on an exterior surface thereof. The marked surface is covered with an overlayer of material to fill the engraved markings and provide a surface suitable for re-marking. The covering material may be applied in a flowabl...
Improved microsensors are provided by combining surface micromachined substrates, including integrated CMOS circuitry, together with bulk micromachined wafer bonded substrates which include at least part of a microelectromechanical sensing element. In the case of an accelerometer, the proof mass is included within the ...
The invention relates to a process for forming an integrated circuit device comprising (i) a substrate; (ii) metallic circuit lines positioned on the substrate and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises porous organic polysilica....
An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first ...
A tape for use in tape-automated-bonding of integrated circuits is disclosed. A series of interconnection arrays ("frames") are arranged along the tape, each array being formed by a number of interconnection beams 3. A terminal ("bump") 6 is located on each beam 3 for bonding to a respective interconnec...
A hybrid integrated circuit is provided that has a monocrystalline substrate such as silicon and a compound semiconductor layer such as gallium arsenide or indium phosphide. An optical communications port may be formed on the hybrid integrated circuit. Electrical equipment may be provided that includes electrical compo...
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines ...
A self-aligning process for fabrication of integrated circuits utilizing ion implantation to effect doping. A composed masking technique is used to define self-aligned areas in a silicon oxide layer for definition of isolation, base, resistor and collector contact regions. Only two oxide removal steps are required for ...
An integrated thin-film solar battery having a plurality of unit elements connected in series includes a substrate, a plurality of spaced apart first electrode layers formed on the substrate; a plurality of semiconductor layers disposed on said plurality of first electrode layers in such a manner that each of the semic...
A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to fo...